diff --git a/ElectroPepper_temp_1.kicad_pcb b/ElectroPepper_temp_1.kicad_pcb new file mode 100644 index 0000000..1a32902 --- /dev/null +++ b/ElectroPepper_temp_1.kicad_pcb @@ -0,0 +1,136 @@ +(kicad_pcb (version 20171130) (host pcbnew 5.1.10) + + (general + (thickness 1.6) + (drawings 0) + (tracks 0) + (zones 0) + (modules 0) + (nets 1) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.25) + (user_trace_width 0.3) + (user_trace_width 0.4) + (user_trace_width 0.5) + (user_trace_width 0.6) + (trace_clearance 0.1) + (zone_clearance 0.4) + (zone_45_only no) + (trace_min 0.2) + (via_size 0.6) + (via_drill 0.3) + (via_min_size 0.4) + (via_min_drill 0.3) + (user_via 0.6 0.3) + (user_via 0.8 0.5) + (uvia_size 0.6) + (uvia_drill 0.3) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (edge_width 0.15) + (segment_width 0.2) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 0.6 0.6) + (mod_text_width 0.1) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0.2) + (aux_axis_origin 0 0) + (visible_elements 7FFFFFFF) + (pcbplotparams + (layerselection 0x010f0_80000001) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue false) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 0) + (scaleselection 1) + (outputdirectory "C:/Users/Ricardo.MARAS/Desktop/Stuff/Sveins/NMM-1/NMM1_Kicad/gerbers/")) + ) + + (net 0 "") + + (net_class Default "This is the default net class." + (clearance 0.1) + (trace_width 0.25) + (via_dia 0.6) + (via_drill 0.3) + (uvia_dia 0.6) + (uvia_drill 0.3) + ) + + (net_class "Main 1" "" + (clearance 0.1) + (trace_width 0.4) + (via_dia 0.6) + (via_drill 0.3) + (uvia_dia 0.6) + (uvia_drill 0.3) + ) + + (net_class "Main 2" "" + (clearance 0.1) + (trace_width 0.5) + (via_dia 0.6) + (via_drill 0.3) + (uvia_dia 0.6) + (uvia_drill 0.3) + ) + + (net_class "Power 1" "" + (clearance 0.1) + (trace_width 0.6) + (via_dia 0.8) + (via_drill 0.5) + (uvia_dia 0.8) + (uvia_drill 0.5) + ) + +) diff --git a/ElectroPepper_temp_1.pro b/ElectroPepper_temp_1.pro new file mode 100644 index 0000000..b89b1c1 --- /dev/null +++ b/ElectroPepper_temp_1.pro @@ -0,0 +1,276 @@ +update=fim 15.júl 2021, 17:06:49 +version=1 +last_client=kicad +[cvpcb] +version=1 +NetIExt=net +[general] +version=1 +[eeschema] +version=1 +LibDir= +[pcbnew] +version=1 +PageLayoutDescrFile= +LastNetListRead= +CopperLayerCount=2 +BoardThickness=1.6 +AllowMicroVias=0 +AllowBlindVias=0 +RequireCourtyardDefinitions=0 +ProhibitOverlappingCourtyards=1 +MinTrackWidth=0.2 +MinViaDiameter=0.4 +MinViaDrill=0.3 +MinMicroViaDiameter=0.2 +MinMicroViaDrill=0.09999999999999999 +MinHoleToHole=0.25 +TrackWidth1=0.25 +TrackWidth2=0.3 +TrackWidth3=0.4 +TrackWidth4=0.5 +TrackWidth5=0.6 +ViaDiameter1=0.6 +ViaDrill1=0.3 +ViaDiameter2=0.6 +ViaDrill2=0.3 +ViaDiameter3=0.8 +ViaDrill3=0.5 +dPairWidth1=0.2 +dPairGap1=0.25 +dPairViaGap1=0.25 +SilkLineWidth=0.15 +SilkTextSizeV=0.6 +SilkTextSizeH=0.6 +SilkTextSizeThickness=0.09999999999999999 +SilkTextItalic=0 +SilkTextUpright=1 +CopperLineWidth=0.2 +CopperTextSizeV=1.5 +CopperTextSizeH=1.5 +CopperTextThickness=0.3 +CopperTextItalic=0 +CopperTextUpright=1 +EdgeCutLineWidth=0.15 +CourtyardLineWidth=0.05 +OthersLineWidth=0.15 +OthersTextSizeV=1 +OthersTextSizeH=1 +OthersTextSizeThickness=0.15 +OthersTextItalic=0 +OthersTextUpright=1 +SolderMaskClearance=0.2 +SolderMaskMinWidth=0 +SolderPasteClearance=0 +SolderPasteRatio=-0 +[pcbnew/Layer.F.Cu] +Name=F.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.In1.Cu] +Name=In1.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In2.Cu] +Name=In2.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In3.Cu] +Name=In3.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In4.Cu] +Name=In4.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In5.Cu] +Name=In5.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In6.Cu] +Name=In6.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In7.Cu] +Name=In7.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In8.Cu] +Name=In8.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In9.Cu] +Name=In9.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In10.Cu] +Name=In10.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In11.Cu] +Name=In11.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In12.Cu] +Name=In12.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In13.Cu] +Name=In13.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In14.Cu] +Name=In14.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In15.Cu] +Name=In15.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In16.Cu] +Name=In16.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In17.Cu] +Name=In17.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In18.Cu] +Name=In18.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In19.Cu] +Name=In19.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In20.Cu] +Name=In20.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In21.Cu] +Name=In21.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In22.Cu] +Name=In22.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In23.Cu] +Name=In23.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In24.Cu] +Name=In24.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In25.Cu] +Name=In25.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In26.Cu] +Name=In26.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In27.Cu] +Name=In27.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In28.Cu] +Name=In28.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In29.Cu] +Name=In29.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In30.Cu] +Name=In30.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.B.Cu] +Name=B.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.B.Adhes] +Enabled=1 +[pcbnew/Layer.F.Adhes] +Enabled=1 +[pcbnew/Layer.B.Paste] +Enabled=1 +[pcbnew/Layer.F.Paste] +Enabled=1 +[pcbnew/Layer.B.SilkS] +Enabled=1 +[pcbnew/Layer.F.SilkS] +Enabled=1 +[pcbnew/Layer.B.Mask] +Enabled=1 +[pcbnew/Layer.F.Mask] +Enabled=1 +[pcbnew/Layer.Dwgs.User] +Enabled=1 +[pcbnew/Layer.Cmts.User] +Enabled=1 +[pcbnew/Layer.Eco1.User] +Enabled=1 +[pcbnew/Layer.Eco2.User] +Enabled=1 +[pcbnew/Layer.Edge.Cuts] +Enabled=1 +[pcbnew/Layer.Margin] +Enabled=1 +[pcbnew/Layer.B.CrtYd] +Enabled=1 +[pcbnew/Layer.F.CrtYd] +Enabled=1 +[pcbnew/Layer.B.Fab] +Enabled=1 +[pcbnew/Layer.F.Fab] +Enabled=1 +[pcbnew/Layer.Rescue] +Enabled=0 +[pcbnew/Netclasses] +[pcbnew/Netclasses/Default] +Name=Default +Clearance=0.1 +TrackWidth=0.25 +ViaDiameter=0.6 +ViaDrill=0.3 +uViaDiameter=0.6 +uViaDrill=0.3 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25 +[pcbnew/Netclasses/1] +Name=Main 1 +Clearance=0.1 +TrackWidth=0.4 +ViaDiameter=0.6 +ViaDrill=0.3 +uViaDiameter=0.6 +uViaDrill=0.3 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25 +[pcbnew/Netclasses/2] +Name=Main 2 +Clearance=0.1 +TrackWidth=0.5 +ViaDiameter=0.6 +ViaDrill=0.3 +uViaDiameter=0.6 +uViaDrill=0.3 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25 +[pcbnew/Netclasses/3] +Name=Power 1 +Clearance=0.1 +TrackWidth=0.6 +ViaDiameter=0.8 +ViaDrill=0.5 +uViaDiameter=0.8 +uViaDrill=0.5 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25 diff --git a/ElectroPepper_temp_1.sch b/ElectroPepper_temp_1.sch new file mode 100644 index 0000000..ba53e41 --- /dev/null +++ b/ElectroPepper_temp_1.sch @@ -0,0 +1,16 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "NMM-1" +Date "" +Rev "A" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$EndSCHEMATC diff --git a/fp-info-cache b/fp-info-cache new file mode 100644 index 0000000..573541a --- /dev/null +++ b/fp-info-cache @@ -0,0 +1 @@ +0