NMM-1/NMM1_Kicad/nmm1.bak

EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:nmm1-cache
EELAYER 25 0
EELAYER END
$Descr A3 16535 11693
encoding utf-8
Sheet 1 1
Title "NMM 1"
Date ""
Rev "A"
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L ATMEGA328PB-A IC?
U 1 1 58A43BF6
P 8050 5550
F 0 "IC?" H 7025 6925 50  0000 R BNN
F 1 "ATMEGA328PB-A" H 9150 4125 50  0000 R BNN
F 2 "Housings_QFP:TQFP-32_7x7mm_Pitch0.8mm" H 8000 4150 50  0001 L CIN
F 3 "" H 7750 5600 50  0000 C CNN
	1    8050 5550
	1    0    0    -1  
$EndComp
$Comp
L Crystal Y?
U 1 1 58A43D5E
P 10050 5000
F 0 "Y?" V 9900 5100 50  0000 C CNN
F 1 "8MHZ" V 10350 5000 50  0000 C CNN
F 2 "" H 10050 5000 50  0000 C CNN
F 3 "" H 10050 5000 50  0000 C CNN
	1    10050 5000
	0    1    1    0   
$EndComp
$Comp
L C C?
U 1 1 58A45068
P 10400 4750
F 0 "C?" V 10350 4600 50  0000 L CNN
F 1 "22pF" V 10550 4650 50  0000 L CNN
F 2 "Capacitors_SMD:C_0805" H 10438 4600 50  0001 C CNN
F 3 "" H 10400 4750 50  0000 C CNN
	1    10400 4750
	0    1    1    0   
$EndComp
$Comp
L C C?
U 1 1 58A450AC
P 10400 5250
F 0 "C?" V 10450 5300 50  0000 L CNN
F 1 "22pF" V 10250 5150 50  0000 L CNN
F 2 "Capacitors_SMD:C_0805" H 10438 5100 50  0001 C CNN
F 3 "" H 10400 5250 50  0000 C CNN
	1    10400 5250
	0    -1   -1   0   
$EndComp
Wire Wire Line
	9350 4950 9850 4950
Wire Wire Line
	9850 4950 9850 4750
Wire Wire Line
	9850 4750 10250 4750
Wire Wire Line
	9350 5050 9850 5050
Wire Wire Line
	9850 5050 9850 5250
Wire Wire Line
	9850 5250 10250 5250
Wire Wire Line
	10550 4750 10650 4750
Wire Wire Line
	10650 4750 10650 5300
Wire Wire Line
	10550 5250 10650 5250
Connection ~ 10650 5250
Wire Wire Line
	10050 5150 10050 5250
Connection ~ 10050 5250
Wire Wire Line
	10050 4850 10050 4750
Connection ~ 10050 4750
$Comp
L GND #PWR?
U 1 1 58A4518D
P 10650 5300
F 0 "#PWR?" H 10650 5050 50  0001 C CNN
F 1 "GND" H 10650 5150 50  0000 C CNN
F 2 "" H 10650 5300 50  0000 C CNN
F 3 "" H 10650 5300 50  0000 C CNN
	1    10650 5300
	1    0    0    -1  
$EndComp
$Comp
L GND #PWR?
U 1 1 58A4619A
P 7950 7150
F 0 "#PWR?" H 7950 6900 50  0001 C CNN
F 1 "GND" H 7950 7000 50  0000 C CNN
F 2 "" H 7950 7150 50  0000 C CNN
F 3 "" H 7950 7150 50  0000 C CNN
	1    7950 7150
	1    0    0    -1  
$EndComp
Wire Wire Line
	7950 7050 7950 7150
Wire Wire Line
	7850 7050 7850 7100
Wire Wire Line
	7850 7100 7950 7100
Connection ~ 7950 7100
Wire Wire Line
	6750 4650 6700 4650
Wire Wire Line
	6700 4650 6700 4725
$Comp
L GND #PWR?
U 1 1 58A4637C
P 6700 4725
F 0 "#PWR?" H 6700 4475 50  0001 C CNN
F 1 "GND" H 6700 4575 50  0000 C CNN
F 2 "" H 6700 4725 50  0000 C CNN
F 3 "" H 6700 4725 50  0000 C CNN
	1    6700 4725
	1    0    0    -1  
$EndComp
$EndSCHEMATC
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`EESchema Schematic File Version 2`
			`LIBS:power`
			`LIBS:device`
			`LIBS:transistors`
			`LIBS:conn`
			`LIBS:linear`
			`LIBS:regul`
			`LIBS:74xx`
			`LIBS:cmos4000`
			`LIBS:adc-dac`
			`LIBS:memory`
			`LIBS:xilinx`
			`LIBS:microcontrollers`
			`LIBS:dsp`
			`LIBS:microchip`
			`LIBS:analog_switches`
			`LIBS:motorola`
			`LIBS:texas`
			`LIBS:intel`
			`LIBS:audio`
			`LIBS:interface`
			`LIBS:digital-audio`
			`LIBS:philips`
			`LIBS:display`
			`LIBS:cypress`
			`LIBS:siliconi`
			`LIBS:opto`
			`LIBS:atmel`
			`LIBS:contrib`
			`LIBS:valves`
			`LIBS:nmm1-cache`
			`EELAYER 25 0`
			`EELAYER END`
			`$Descr A3 16535 11693`
			`encoding utf-8`
			`Sheet 1 1`
			`Title "NMM 1"`
			`Date ""`
			`Rev "A"`
			`Comp ""`
			`Comment1 ""`
			`Comment2 ""`
			`Comment3 ""`
			`Comment4 ""`
			`$EndDescr`
			`$Comp`
			`L ATMEGA328PB-A IC?`
			`U 1 1 58A43BF6`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`P 8050 5550`
			`F 0 "IC?" H 7025 6925 50 0000 R BNN`
			`F 1 "ATMEGA328PB-A" H 9150 4125 50 0000 R BNN`
			`F 2 "Housings_QFP:TQFP-32_7x7mm_Pitch0.8mm" H 8000 4150 50 0001 L CIN`
			`F 3 "" H 7750 5600 50 0000 C CNN`
			`1 8050 5550`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`1 0 0 -1`
			`$EndComp`
			`$Comp`
			`L Crystal Y?`
			`U 1 1 58A43D5E`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`P 10050 5000`
			`F 0 "Y?" V 9900 5100 50 0000 C CNN`
			`F 1 "8MHZ" V 10350 5000 50 0000 C CNN`
			`F 2 "" H 10050 5000 50 0000 C CNN`
			`F 3 "" H 10050 5000 50 0000 C CNN`
			`1 10050 5000`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`0 1 1 0`
			`$EndComp`
			`$Comp`
			`L C C?`
			`U 1 1 58A45068`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`P 10400 4750`
			`F 0 "C?" V 10350 4600 50 0000 L CNN`
			`F 1 "22pF" V 10550 4650 50 0000 L CNN`
			`F 2 "Capacitors_SMD:C_0805" H 10438 4600 50 0001 C CNN`
			`F 3 "" H 10400 4750 50 0000 C CNN`
			`1 10400 4750`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`0 1 1 0`
			`$EndComp`
			`$Comp`
			`L C C?`
			`U 1 1 58A450AC`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`P 10400 5250`
			`F 0 "C?" V 10450 5300 50 0000 L CNN`
			`F 1 "22pF" V 10250 5150 50 0000 L CNN`
			`F 2 "Capacitors_SMD:C_0805" H 10438 5100 50 0001 C CNN`
			`F 3 "" H 10400 5250 50 0000 C CNN`
			`1 10400 5250`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`0 -1 -1 0`
			`$EndComp`
			`Wire Wire Line`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`9350 4950 9850 4950`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`Wire Wire Line`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`9850 4950 9850 4750`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`Wire Wire Line`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`9850 4750 10250 4750`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`Wire Wire Line`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`9350 5050 9850 5050`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`Wire Wire Line`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`9850 5050 9850 5250`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`Wire Wire Line`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`9850 5250 10250 5250`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`Wire Wire Line`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`10550 4750 10650 4750`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`Wire Wire Line`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`10650 4750 10650 5300`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`Wire Wire Line`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`10550 5250 10650 5250`
			`Connection ~ 10650 5250`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`Wire Wire Line`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`10050 5150 10050 5250`
			`Connection ~ 10050 5250`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`Wire Wire Line`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`10050 4850 10050 4750`
			`Connection ~ 10050 4750`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`$Comp`
			`L GND #PWR?`
			`U 1 1 58A4518D`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`P 10650 5300`
			`F 0 "#PWR?" H 10650 5050 50 0001 C CNN`
			`F 1 "GND" H 10650 5150 50 0000 C CNN`
			`F 2 "" H 10650 5300 50 0000 C CNN`
			`F 3 "" H 10650 5300 50 0000 C CNN`
			`1 10650 5300`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`1 0 0 -1`
			`$EndComp`
			`$Comp`
			`L GND #PWR?`
			`U 1 1 58A4619A`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`P 7950 7150`
			`F 0 "#PWR?" H 7950 6900 50 0001 C CNN`
			`F 1 "GND" H 7950 7000 50 0000 C CNN`
			`F 2 "" H 7950 7150 50 0000 C CNN`
			`F 3 "" H 7950 7150 50 0000 C CNN`
			`1 7950 7150`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`1 0 0 -1`
			`$EndComp`
			`Wire Wire Line`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`7950 7050 7950 7150`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`Wire Wire Line`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`7850 7050 7850 7100`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`Wire Wire Line`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`7850 7100 7950 7100`
			`Connection ~ 7950 7100`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`Wire Wire Line`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`6750 4650 6700 4650`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`Wire Wire Line`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`6700 4650 6700 4725`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`$Comp`
			`L GND #PWR?`
			`U 1 1 58A4637C`
Minor schematic changes. 2017-02-15 11:55:32 +00:00			`P 6700 4725`
			`F 0 "#PWR?" H 6700 4475 50 0001 C CNN`
			`F 1 "GND" H 6700 4575 50 0000 C CNN`
			`F 2 "" H 6700 4725 50 0000 C CNN`
			`F 3 "" H 6700 4725 50 0000 C CNN`
			`1 6700 4725`
First commit, generated basic files and started schematic. 2017-02-15 11:41:20 +00:00			`1 0 0 -1`
			`$EndComp`
			`$EndSCHEMATC`