Almost finished placing and connecting.

pcb/RevA/rste-cache.lib

@@ -1,6 +1,22 @@
 EESchema-LIBRARY Version 2.3
 #encoding utf-8
 #
+# +3V3
+#
+DEF +3V3 #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "+3V3" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS +3.3V
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +3V3 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
 # +5V
 #
 DEF +5V #PWR 0 0 Y Y 1 F P
@@ -82,6 +98,29 @@ X ~ 2 0 -150 110 U 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
+# CP
+#
+DEF CP C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "CP" 25 -100 50 H V L CNN
+F2 "" 38 -150 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ CP_*
+$ENDFPLIST
+DRAW
+S -90 20 -90 40 0 1 0 N
+S -90 20 90 20 0 1 0 N
+S 90 -20 -90 -40 0 1 0 F
+S 90 40 -90 40 0 1 0 N
+S 90 40 90 20 0 1 0 N
+P 2 0 1 0 -70 90 -30 90 N
+P 2 0 1 0 -50 110 -50 70 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 110 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
 # CP_Small
 #
 DEF CP_Small C 0 10 N N 1 F N
@@ -468,7 +507,7 @@ ENDDEF
 #
 # SN75172
 #
-DEF SN75172 U 0 40 Y Y 4 F N
+DEF SN75172 U 0 20 Y Y 4 F N
 F0 "U" -150 200 47 H V C CNN
 F1 "SN75172" 200 -200 47 H V C CNN
 F2 "" 0 -50 47 H I C CNN
@@ -477,14 +516,16 @@ $FPLIST
  SOIC-20
 $ENDFPLIST
 DRAW
-T 0 40 110 20 0 0 0 "g/~g" Normal 0 C C
+T 0 40 110 20 0 0 0 "g|~g" Normal 0 C C
 C 110 -30 10 0 1 0 N
 S -200 150 200 -150 0 1 0 f
-P 2 0 1 0 0 0 -25 0 N
+P 2 0 1 0 0 0 -100 0 N
 P 2 0 1 0 40 30 40 80 N
 P 2 0 1 0 100 25 150 25 N
 P 2 0 1 0 100 50 100 -50 N
 P 2 0 1 0 120 -30 150 -30 N
+P 2 0 1 0 150 -30 200 -100 N
+P 2 0 1 0 150 25 200 100 N
 P 4 0 1 0 0 50 100 0 0 -50 0 50 N
 X 1A 1 -350 0 150 R 40 40 1 1 B
 X 1Y 2 350 100 150 L 40 40 1 1 B