build/esp-idf/esp_driver_spi/libesp_driver_spi.a

!<arch>
/               0           0     0     0       1512      `
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spi_common.c.obj/
spi_master.c.obj/
/0              0           0     0     644     160340    `
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E (%lu) %s: sclk pin required.
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E (%lu) %s: both wp and hd required.
E (%lu) %s: not using iomux pins
E (%lu) %s: %s(%d): not all required capabilities satisfied.
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E (%lu) %s: %s(%d): Failed to allocate priv %s buffer
E (%lu) %s: %s(%d): sync failed for %s buffer
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E (%lu) %s: %s(%d): SPI bus already initialized.
E (%lu) %s: %s(%d): invalid dma channel
E (%lu) %s: %s(%d): intr flag not allowed
E (%lu) %s: %s(%d): no support changing io default level 
spi masterE (%lu) %s: %s(%d): alloc host failed
E (%lu) %s: power down peripheral in sleep is not enabled or not supported on your target
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E (%lu) %s: %s(%d): SPI Master cannot attach to bus. (Check CONFIG_SPI_FLASH_SHARE_SPI1_BUS)
E (%lu) %s: %s(%d): invalid core id
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dev != NULL//IDF/components/esp_driver_spi/src/gpspi/spi_master.cspi_hal_usr_is_done(&host->hal)host->cur_cs != DEV_NUM_MAXhost->cur_cs == DEV_NUM_MAXdesired_devE (%lu) %s: %s(%d): invalid dev handle
E (%lu) %s: %s(%d): SPI_TRANS_USE_RXDATA only available for rxdata transfer <= 32 bits
E (%lu) %s: %s(%d): SPI_TRANS_USE_TXDATA only available for txdata transfer <= 32 bits
E (%lu) %s: %s(%d): txdata transfer > host maximum
E (%lu) %s: %s(%d): rxdata transfer > host maximum
E (%lu) %s: %s(%d): rx length > tx length in full duplex mode
E (%lu) %s: %s(%d): Incompatible when setting to both multi-line mode and 3-wire-mode
E (%lu) %s: %s(%d): Incompatible when setting to both multi-line mode and half duplex mode
E (%lu) %s: %s(%d): SPI half duplex mode does not support using DMA with both MOSI and MISO phases.
E (%lu) %s: %s(%d): rx unaligned byte with DMA is not supported
E (%lu) %s: %s(%d): trans tx_buffer should be NULL and SPI_TRANS_USE_TXDATA should be cleared to skip MOSI phase.
E (%lu) %s: %s(%d): trans rx_buffer should be NULL and SPI_TRANS_USE_RXDATA should be cleared to skip MISO phase.
E (%lu) %s: %s(%d): Dummy phase is not available when both data out and in are enabled
E (%lu) %s: %s(%d): txdata transfer > hardware max supported len
E (%lu) %s: %s(%d): rxdata transfer > hardware max supported len
E (%lu) %s: %s(%d): Using PSRAM must when cache is enabled
E (%lu) %s: %s(%d): acquire finite time not supported now.
E (%lu) %s: %s(%d): Cannot acquire bus when a polling transaction is in progress.
E (%lu) %s: Cannot release bus when a polling transaction is in progress.
0ret == ESP_OKE (%lu) %s: %s(%d): currently timeout is not available for polling transactions
E (%lu) %s: %s(%d): Cannot send polling transaction while the previous polling transaction is not terminated.
E (%lu) %s: polling can't get buslock
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clk_tree_defs.h	spi_types.hspi_common.hdma_types.h
spi_dma.hspi_struct.hspi_share_hw_ctrl.hspi_common_internal.hspi_master.hesp_clk_tree.hesp_log_config.hspinlock.hportmacro.hqueue.hspi_ll.hspi_hal.htask.hcache_utils.hesp_memory_utils.hesp_log.hperiph_ctrl.hassert.hesp_intr_alloc.hstdlib.hstring.hesp_heap_caps.hesp_clk_tree_common.hesp_rom_sys.hesp_log_timestamp.h<built-in><03>				!			!			1			2													?				'							@				(							A				)			'	O			-	%							-	%					,	$					<03>						+		l	B				'	]									E	P							<03>						'	o		'	%			<03>				&		
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+@T<>p<00>?<00>)<00>:@Ĭ|<00><00>N<00>*$I@@<40><<00><00>]<00>*qX@|<7C><00><00><00><00>X+ <00>x+<00><00>+<00><00>+<00><00>+<00><00>+<00>+,/$,F8,]P,ul,<00><00>,<00><00>,<00><00>,	<00><00>,<00><00>,<00><00>,	-%	-3	-<00>.	@`<60>P<00><00>E	0<00>f@	@<00><>Y<00><00>Q	<00><><00>d	ʜv_	@<00>d <00><00>t	@<40>o	@1<00><00><00><00>	P<>8<00>	@4`<00><00><00>	<00><>zS<00>	@l74b<00><00><00>	0%/<00>	0':0<00>	W:8<00>	<00>:<00><00>	@<00><>h<00><00><00>	;0<00>	@<08>0<00><00><00>P<00><00><00>	P_<00>	8<><00>	spi_slave.c.obj/0           0     0     644     136556    `
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<EFBFBD><00><1D>6A<00><><EFBFBD><1B>s{<7B><1D><>A<EFBFBD><00><00>2<EFBFBD>B<EFBFBD>R<EFBFBD><00><00><03><00><00>¨2<C2A8>B<EFBFBD>R<EFBFBD><00><00><><EFBFBD>+<2B>c{<7B>Ҡ<00><>A<EFBFBD><41><EFBFBD><00><00><02><12>"<22><00><00><03><00>ز<><02><12>"<22><00><1D>6Ar<>,<2C>"<22>P<>ؽ<07>"<03><00><00><07><00><1B><07><00><00><07><00><00><07><00><1D>6A<00>x<><78><EFBFBD>y<><79>L<EFBFBD><00><><EFBFBD><EFBFBD> <00><08><><EFBFBD><7F><10> <00>F<00><08>y<>B<EFBFBD><00><1D>spi_slave_hal_usr_is_done(hal)//IDF/components/esp_driver_spi/src/gpspi/spi_slave.cpriv_trans.transspi_slaveW (%lu) %s: Use DMA but real trans_len is not 4 bytes aligned, slave may loss data
E (%lu) %s: %s(%d): 
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<EFBFBD><EFBFBD><EFBFBD><03><07><00><1D>E (%lu) %s: %s(%d): invalid host
E (%lu) %s: %s(%d): host not slave
6a<00>2)<29><00><00><00><>D<EFBFBD><01><00><0B><> <20><00><><01><00>"<22><02>,<00><00><><EFBFBD><EFBFBD>영<00><00><00><>E<EFBFBD><01><00><0B><> <20><00><><01><00>"<22><02><00>(Z<00><00><00><00><><EFBFBD><EFBFBD><08>(Z<00><00><00><00><><EFBFBD><EFBFBD><08>(<28>P<>h<EFBFBD><02><00><00><02><00><00><00><><EFBFBD><EFBFBD><08>H<EFBFBD><48><00>(<28><>@<40><00>qpr<70><72><07><><EFBFBD><00><00><07><00><08><07><02><00><1D>E (%lu) %s: %s(%d): invalid dma channel
E (%lu) %s: %s(%d): intr flag not allowed
E (%lu) %s: %s(%d): spics pin invalid
E (%lu) %s: %s(%d): use feature flag 'SPI_SLAVE_NO_RETURN_RESULT' but no post_trans_cb function sets
spi slaveE (%lu) %s: %s(%d): host already in use
E (%lu) %s: power down peripheral in sleep is not enabled or not supported on your target
E (%lu) %s: %s(%d): invalid core id
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