Reflow-plate/build/esp-idf/esp_hal_i2s/libesp_hal_i2s.a

!<arch>
/               0           0     0     0       382       `


Pi2s_hal_calc_mclk_precise_divisioni2s_hal_initi2s_hal_set_tx_clock_i2s_hal_set_rx_clocki2s_hal_std_set_tx_sloti2s_hal_std_set_rx_sloti2s_hal_std_enable_tx_channeli2s_hal_std_enable_rx_channeli2s_hal_pdm_set_tx_sloti2s_hal_pdm_enable_tx_channeli2s_hal_pdm_set_rx_sloti2s_hal_pdm_enable_rx_channeli2s_periph_signal//                                              18        `
i2s_periph.c.obj/
i2s_hal.c.obj/  0           0     0     644     69892     `
ELF



^
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_default_types.h_stdint.hinterrupts.hclk_tree_defs.hi2s_periph.hmck_in_sigETS_RWBLE_INTR_SOURCEETS_PWM0_INTR_SOURCEETS_MPU_IA_INTR_SOURCEs_rx_bck_sigETS_TG1_T0_LEVEL_INTR_SOURCEETS_TG0_T1_LEVEL_INTR_SOURCEcharETS_I2S0_INTR_SOURCEshort intdata_in_sigETS_SPI2_INTR_SOURCEETS_FROM_CPU_INTR3_SOURCEm_rx_bck_sigm_tx_bck_sigETS_TG1_T1_LEVEL_INTR_SOURCEETS_MAX_INTR_SOURCEdata_out_sigETS_CACHE_IA_INTR_SOURCEETS_BT_BB_NMI_SOURCEETS_WDT_INTR_SOURCEuint8_tETS_EFUSE_INTR_SOURCEETS_TG1_T1_EDGE_INTR_SOURCEETS_UART1_INTR_SOURCEETS_GPIO_INTR_SOURCEETS_TG0_LACT_EDGE_INTR_SOURCEETS_SPI3_DMA_INTR_SOURCEETS_LEDC_INTR_SOURCElong long ints_rx_ws_sigETS_RWBT_NMI_SOURCEETS_TWAI_INTR_SOURCESOC_MOD_CLK_XTAL32KSOC_MOD_CLK_RTC_FASTi2s_periph_signallong intETS_TG0_WDT_LEVEL_INTR_SOURCEETS_TG1_LACT_LEVEL_INTR_SOURCEmck_out_sigETS_MMU_IA_INTR_SOURCEETS_TG1_LACT_EDGE_INTR_SOURCESOC_MOD_CLK_RTC_SLOW__uint8_tETS_TG1_T0_EDGE_INTR_SOURCEETS_UHCI0_INTR_SOURCESOC_MOD_CLK_REF_TICKs_tx_ws_sigSOC_MOD_CLK_APLLETS_ETH_MAC_INTR_SOURCEETS_FROM_CPU_INTR1_SOURCEETS_SDIO_HOST_INTR_SOURCElong doubleETS_GPIO_NMI_SOURCE/home/ricardo/.espressif/v6.1/esp-idf/components/esp_hal_i2s/esp32/i2s_periph.cunsigned charETS_TG0_LACT_LEVEL_INTR_SOURCESOC_MOD_CLK_INVALIDETS_TIMER1_INTR_SOURCEETS_UART2_INTR_SOURCEsigned charSOC_MOD_CLK_PLL_D2long long unsigned intETS_TIMER2_INTR_SOURCEunsigned intdata_out_sigsETS_SPI0_INTR_SOURCEETS_TG0_WDT_EDGE_INTR_SOURCEETS_FROM_CPU_INTR0_SOURCEETS_WIFI_BB_INTR_SOURCEshort unsigned intETS_RMT_INTR_SOURCE_BoolSOC_MOD_CLK_CPUETS_TG1_WDT_EDGE_INTR_SOURCEETS_UHCI1_INTR_SOURCEETS_RWBT_INTR_SOURCEETS_BT_BB_INTR_SOURCEETS_RTC_CORE_INTR_SOURCEdata_in_sigsETS_RSA_INTR_SOURCEETS_I2S1_INTR_SOURCEETS_SLC1_INTR_SOURCEETS_SPI1_DMA_INTR_SOURCEi2s_signal_conn_tETS_I2C_EXT0_INTR_SOURCEGNU C23 15.2.0 -ftls-model=local-exec -mdynconfig=xtensa_esp32.so -mlongcalls -gdwarf-4 -ggdb -Og -std=gnu23 -fno-builtin-memcpy -fno-builtin-memset -fno-builtin-bzero -ffunction-sections -fdata-sections -fno-shrink-wrap -fstrict-volatile-bitfields -fno-jump-tables -fno-tree-switch-conversion -fzero-init-padding-bits=all -fno-malloc-dcelong unsigned intETS_BT_MAC_INTR_SOURCESOC_MOD_CLK_RC_FAST_D256ETS_SPI2_DMA_INTR_SOURCEETS_PWM1_INTR_SOURCEETS_FROM_CPU_INTR2_SOURCESOC_MOD_CLK_APBETS_WIFI_MAC_NMI_SOURCESOC_MOD_CLK_XTAL/home/ricardo/ElectroNext/Projects/Reflow plate/esp-idf-firmware/Reflow-plate/buildETS_SPI1_INTR_SOURCEs_tx_bck_sigETS_TG0_T0_EDGE_INTR_SOURCEETS_SPI3_INTR_SOURCEETS_TG0_T1_EDGE_INTR_SOURCESOC_MOD_CLK_PLL_F160MSOC_MOD_CLK_RC_FASTETS_RWBLE_NMI_SOURCEm_rx_ws_sigETS_WIFI_MAC_INTR_SOURCEETS_TG1_WDT_LEVEL_INTR_SOURCEETS_SLC0_INTR_SOURCEETS_I2C_EXT1_INTR_SOURCEETS_TG0_T0_LEVEL_INTR_SOURCEETS_PCNT_INTR_SOURCEETS_UART0_INTR_SOURCEm_tx_ws_sigGCC: (crosstool-NG esp-15.2.0_20251204) 15.2.0 
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