Reflow-plate/build/esp-idf/esp_hal_timg/libesp_hal_timg.a

!<arch>
/               0           0     0     0       150       `

*
*
*
*\6timer_hal_inittimer_hal_deinittimer_hal_set_counter_valuetimer_hal_capture_and_get_counter_valuesoc_timg_gptimer_signals//                                              20        `
timer_periph.c.obj/
timer_hal.c.obj/0           0     0     644     23248     `
ELF



^
<00>T4(&%<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><00>6A<00>S<EFBFBD><00><00><00>I@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <00>	<09><><EFBFBD><EFBFBD>A<EFBFBD> <00>	<09>@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <00><08><00><><10> <00><08>@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <00><08><><EFBFBD><EFBFBD><EFBFBD><10> <00>M<08> <00><08><00><><10> <00><1D>6A<00><02><12><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <00><08><><EFBFBD><EFBFBD>A<EFBFBD> <00><08><02><12><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <00><08><00><><10> <00><08><02><12><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <00>	«<><C2AB><EFBFBD><10> <00>	<09>	<09> <00>	<09><00><><10> <00><08><1D>6A<00><02><12><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <00>y<EFBFBD> <00>i<EFBFBD> Yy<59> Ii<49><02><12><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><19> <00><><EFBFBD><02><12><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <00>y<EFBFBD> <00>i<1D>6A<00><02><12><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <00>8<EFBFBD><00><> <20> <00>8<EFBFBD><38><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <00>8<EFBFBD><18><><02><12><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 8)<29> (<1D><00><><EFBFBD><EFBFBD>
|
l h H A 

*
nK<07>

<06>
<08>	<05><07><03>	<03>b	l<03>%int$8.Vx:p
<08><03>
<1C><04>c
<06>S<07><06>!<21><07><06>$ZH<07><06>$<24>L<07><06>$<24>P<07><06>$FT<07><06>$<24>X<06>$<24>\7<06>!'`<07>	<06>%rdz<06>$	h<07><06>%n	l:<06>$c
p0	<06>!<21>
t_<06> 
xJ
<06> U|<06>$<24><00><07><06>%<25><00><07><06>%6<00><07>	<06>$<24><00><06>$<24><00><06>"
<00><07><06>(<28>
<00>y<06>(5<00><07><06>'<27><00><07><06>(S<00>_<06><0E><00>?<06>%<25><00><07>
<06> <00>	w	dev<1A>
<0E>KS
<0C><12>
e
<12>
.
<12>
!<12>
<0C>	%<12>))<12>
<0C>/<12>

<0C>3<12>

	(<0E>val5<0E>f6
(<S<0C>B<12> 
;	n9valD<0E><03>ESnK<05><0C>Q<12> 
J	<09>valS<0E><03>T<03><10>Z<05><0C>[<12>
<0C>_<12>

Y	
<0E>vala<0E>Q
b<03>
h5<0C>l<12> 
g	Pvaln<0E><03>o5Pu{<0C>{<12> 
t	<09>aval}<0E><03>~{<10><06><05>
<06><12> 
<06>	<09><0E>val<06><0E>1<06><03><10><06><0C><06><12> 
<06>	"<0E>val<06><0E><03><06>"<06>M[<06><12> 
<06>	h3val<06><0E><03>
<06>Mh<06>3<0C><06><12>q
<06><12>
<06><12>[	<06><12><0C><06><12>

p	<06><12>
	<0C><06><12><0C><06><12><0C><06><12><0C><06><12>
<0C><06><12>

<06>	Nyval<06><0E>"<06>3N<06><05><0C><06><12><0C>
<06><12>
<06>	<09>_val<06><0E><03><06><03><10>
<05>Q	
<12> 
	<09><0E>val
<0E><15>
<03><10>
#
<12> 
	9val
<0E><15>
9
g<12>#
<12> 
	<09>Kval%
<0E><15>&
g<10>,
<05><12>
0
<12> +
	<09><0E>val2
<0E>n3
<03><10>9
<05>^=
<12> 8
	<0E>val?
<0E>g@
<03>F
H<12>L
<12> E
	e,valN
<0E>O
HeW
<05><12>X
<12><12>\
<12>
$`
<12>)d
<12>

h
<12>
<12>l
<12>
V
		wvaln
<0E>
o
<03>	u
D	<12>v
<12>Oz
<12>t
	a		val|
<0E><15>}
D	a	<06>
9
<12><06>
<12><12>
<06>
<12>
<12>	<06>
<12>
l<06>
<12>
<12><06>
<12>
<12><06>
<12>
<12>	<06>
<12>
<12><06>
<12><12><06>
<12>
z<06>
<12>

5<06>
<12>
<06>
	V
s	val<06>
<0E>;<06>
9
V
<06>
<05>
<12><06>
<12> <06>
<12><06>
	<09>
h
val<06>
<0E><06>
<03>
<10>
<06>
<05>
=<06>
<12> <06>
	<09>
<0E>
val<06>
<0E><15><06>
<03>
<10>
<06>
+2<06>
<12> <06>
	Hval<06>
<0E><15><06>
+H<06>
v<06>
<12> <06>
	<09>Zval<06>
<0E><06>
v<10><06>
<05><12><06>
<12> <06>
	<09><0E>val<06>
<0E><15><06>
<03><10><06>
k<06>
<12> <06>
	)<0E>val<06>
<0E>W<06>
)W	<12> 	t;val<0E><15>
Wt<05><12><12> 	<09><0E>val<0E>A<03><10><05><12>#<12> 	

<0E>val%<0E>}&<03>

.|

2<12>
<12>
6<12>
<12>:<12>
<12>><12>
<12>?<12>-	<09>

valA<0E><15>B|
<10>
HL<12>
PP<12>
<12>T<12>
	X<12>
<12>Y<12>G	(<0E>
val[<0E>Q\(b<05><12>f<12>
0j<12>
<12>n<12>
>
r<12>
<12>s<12>a	<09>:valu<0E>8	v<03><10>|))<06><12>
<12><06><12>
<12><06><12>
p<06><12>
<12><06><12>{	F<0E>val<06><0E><06>)F<06><05>?<06><12>E<06><12><06>	<09>Xval<06><0E><15>	<06><03><10><06><05><12><06><12>
<06><12>
<06>	<09><0E>val<06><0E>^<06><03><10>$<06>	<09>:<06>"4lo<06>zhi<06><1E><07>
<06>"<07><06>#\<07><06>#<23>}<06>"<22><07><06>".6<06> t <15><06><10><18><00>,
<10><18><00>,c<06><03>		<06><13><1A><06><13><1B>
6
<EFBFBD>A
<01><>hal
6G<36>X$
8We-+pB@///
9@WUKljw z
&H
<01><>!hal
&7<>
R"c
&E<>T<>U<>#E
/<0E><00><1D>
/
<1E><00><00><1E><00><00><1D>

0N<00><00><00><00>"<00><00><1D>%%

1<05><1E>

<1E>.
*
<1F>66
3O
M
d
b
"y
w
 <20>
h
<01><>!hal
,<2C>
R}
%<1E><00>
<00>
<1E><00>
<00>
<1E><00>
<00>
<1D>  
f<1E><00>
<00>
<1E><1E>53<1F>::(
<1E>KI<1E>`^us 
l
<01><>!hal
*<2A>
R"


8<>
S$Q	
L<><00><00>}

+<1E><00><00><1E><00><00><1E><00><00><1D>**
l<1E><1E>(&<1E>=;<1F>BB(
<1E>SQ<1E>jf<00><00>%A<02><03>&hw<02>=<3D>'Q	<02>J<EFBFBD><04>(<28>	<02><18><03>&hw<02>><3E>'Q	<02>K<EFBFBD>%<25><02>/&hw<02>:<3A>'Q	<02>G<EFBFBD>'c<02>[<5B>(4<02><18>X&hw<02>?<3F>'Q	<02>L<EFBFBD>%E<02>}&hw<02>><3E>'Q	<02>K<EFBFBD>%<25><02><03>&hw<02>8<EFBFBD>'Q	<02>E<EFBFBD>&en<02>U<EFBFBD>
<02>%r<03>&hwr<<3C>'Q	rI<72>&enrY<72>)5R&hwR6<52>'Q	RC<52>&enRS<52>

%U
$>:;9I$>I
:;9

:;9I8
:;9
	
:;9I8

:;9I8
:;9<0B>


:;9I
8

:;9

I
:;9I5I
:;9<0B>


:;9I
8
:;9

:;9I:;9I
:;9

:;9I8

I
!I/4:;9I?<.
?:;9'I
@<18>B
:;9I<17>B
1R
<01>B
XYW
1<17>B
1R
<01>B
XYW .
?:;9'
@<18>B
!:;9I":;9I#4:;9I<17>B$:;9I<17>B%.
:;9' 
&:;9I':;9I(.
:;9'I 
).
:;9' ?
R?A
<00><03>%<25>,<2C><00>+
Z+
Y/?
Z/?
XHZ<>[<5B>
\
X!
\!
X!T<>U<>%-
Y-2r%(
X(2r6F
\6F
X6FZ<>[<5B>
Yr

X
r0<> +
Y+6r #
X#6r 60<>:b
[:R
X:b0<>Z
TZl
<00><03>%<25>,<2C><00>

X(r
(r
(0<>*5
Y5@r*@
T*@0<>Bj
ZBZ
TZj
<00><03>%<25>,<2C><00>Bj0<>4lhHAlhHA<00>i


<01>






/home/ricardo/.espressif/v6.1/esp-idf/components/esp_hal_timg/home/ricardo/.espressif/v6.1/esp-idf/components/esp_hal_timg/esp32/include/hal/home/ricardo/.espressif/tools/xtensa-esp-elf/esp-15.2.0_20251204/xtensa-esp-elf/picolibc/include/machine/home/ricardo/.espressif/tools/xtensa-esp-elf/esp-15.2.0_20251204/xtensa-esp-elf/picolibc/include/sys/home/ricardo/.espressif/v6.1/esp-idf/components/esp_hal_timg/include/hal/home/ricardo/.espressif/v6.1/esp-idf/components/soc/esp32/register/soctimer_hal.c
timer_ll.h_default_types.h_stdint.htimer_hal.htimer_group_struct.h

	

	
	

	
	
	

	
	
	
<03>	
	
*	
	
	


<03>	
$	
<03>	
	
2	
	
	

<03>	
	
?	
	
0	
	
4	
	
	


B	
	



	
	
 	
	
<03>	
	
*	
	
	
	


<03>	
$	
	
<03>	
	
2	
	
	
	

<03>	
	
	
3	
	
0	
	
4	
	
	

M	
	


	
	


&
	
	
8	
	
<03>
	
	
5	
i	
	

<03>~	
<03>
	
	
/	

	
/	
	

<03>~	
%	
	
<03>
	
	
*	
	
	
	

<03>~	
"	
	
<03>
	
	
/	

	
/	
	


<03>~	
	


6
	

	
&	
	
<03>	
	
.	
	

	

	
*
	

	

	

<03>	
*	
	
<03>	
	
2	
]	
	


<03>	
	

timg_int_clr_timers_reg_tlactloadwdt_stg1_holdtimg_txloadlo_reg_ttimer_ll_trigger_soft_capturetimg_dev_ttimg_wdtconfig5_reg_ttimer_hal_capture_and_get_counter_valuelact_level_int_enwdt_wkeytimg_txalarmhi_reg_twdt_entx_enwdt_int_stalarmhiint_clr_timersunsigned inttimg_rtccalicfg_reg_ttx_level_int_enlact_int_stlacthitimg_txupdate_reg_ttx_alarm_enwdt_flashboot_mod_enwdt_clk_prescalerupdatetimg_txload_reg_tgptimer_soc_handle_tt1_int_enalact_rtc_onlyregclktimg_lactloadlo_reg_twdt_stg3_holdrtc_cali_maxt0_int_rawtimg_wdtconfig0_reg_tuint32_ttimer_ll_trigger_soft_reloadwdt_feedtimg_wdtfeed_reg_trtccalicfgrtccalicfg1hw_timertimg_txloadhi_reg_tlong long unsigned intlactalarmhit1_int_clrtx_hit0_int_sttimg_lactalarmlo_reg_twdt_sys_reset_lengthlact_updatertc_cali_clk_sellact_enlact_loreserved_28timg_int_raw_timers_reg_tlact_alarm_hiint_raw_timerstx_alarm_hilact_autoreloadtimer_hal_deinittimg_wdtconfig2_reg_tlact_loadtimg_txhi_reg_talarmlo_Booltimg_hwtimer_reg_ttimer_idtimer_hal_init__uint64_trtc_cali_rdyloadtimg_lactconfig_reg_twdt_stg0_holdlactlotimg_txconfig_reg_tlact_increasecharlact_load_hirtc_cali_starttx_load_hireserved_0reserved_4lact_int_enartc_cali_start_cyclingtimg_wdtconfig4_reg_ttimer_ll_enable_auto_reloadlact_rtc_step_lenlact_hilactconfigold_reloadt1_int_rawtx_loadload_vallong long inttimer_hal_set_counter_valuetx_increasewdt_level_int_enint_st_timerstimg_rtccalicfg1_reg_tlactalarmlotx_lotimg_txlo_reg_twdt_stg2_holdtimg_lactupdate_reg_tlactloadhitx_autoreloadwdtfeedtimers_date/home/ricardo/ElectroNext/Projects/Reflow plate/esp-idf-firmware/Reflow-plate/buildlact_alarm_lotx_updatetx_alarm_lowdt_int_enawdtconfig0wdtconfig1wdtconfig2wdtconfig3wdtconfig4wdtconfig5timg_lactrtc_reg_tlong doublet1_int_stconfigtimg_lactloadhi_reg_ttimg_lactalarmhi_reg_t/home/ricardo/.espressif/v6.1/esp-idf/components/esp_hal_timg/timer_hal.ctimer_ll_set_reload_valueshort intwdt_int_clrlact_alarm_entimg_lactlo_reg_tlong intlact_load_lotimg_wdtwprotect_reg_ttimer_ll_enable_alarmtimer_hal_context_treserved_0aclact_lac_enuint64_ttimer_ll_enable_counterloadhiwdt_stg0wdt_stg1wdt_stg2wdt_stg3TIMERG1lact_dividertimg_wdtconfig1_reg_ttimg_int_ena_timers_reg_tTIMERG0lact_int_rawlong unsigned intlactrtctimg_int_st_timers_reg_ttimer_numwdt_cpu_reset_lengthwdt_edge_int_enlactloadlowdtwprotecttx_dividerunsigned chartimer_ll_get_reload_value__uint32_ttimg_timers_date_reg_tlact_edge_int_enlact_cpst_engroup_numt0_int_enatx_load_loGNU C23 15.2.0 -ftls-model=local-exec -mdynconfig=xtensa_esp32.so -mlongcalls -gdwarf-4 -ggdb -Og -std=gnu23 -fno-builtin-memcpy -fno-builtin-memset -fno-builtin-bzero -ffunction-sections -fdata-sections -fno-shrink-wrap -fstrict-volatile-bitfields -fno-jump-tables -fno-tree-switch-conversion -fzero-init-padding-bits=all -fno-malloc-dcetimg_lactload_reg_ttimg_wdtconfig3_reg_ttimg_txalarmlo_reg_ttimg_lacthi_reg_twdt_int_rawsigned charshort unsigned intint_ena_timersclk_entx_edge_int_enlactupdatet0_int_clrtimer_ll_get_counter_valuertc_cali_valuetimg_regclk_reg_tlact_int_clrloadloGCC: (crosstool-NG esp-15.2.0_20251204) 15.2.0 
Xtensa_InfoUSE_ABSOLUTE_LITERALS=0
ABI=0



(
`"l(hh(HH($"A
<00><>


!
l,h
=HYA
timer_hal.cTIMERG0TIMERG1timer_hal_inittimer_hal_deinittimer_hal_set_counter_valuetimer_hal_capture_and_get_counter_value

5_+W(;	;	
	
;!;(;	,,
	0
4;9;@;	DD
	H
L;Q;X;	\\
	`
d;i;




!
(
/
6
=
D
K
R
W
e
l
q
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>






-

;

I

W

e

s

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>




)
7
E
j
x
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
)
C
o
<00>
<00>
<00>
<00>

%
Q
k
<00>
<00>
<00>
<00>
#
=
i
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>


#
O
i
y
<00>
<00>
<00>

:
V
<00>
<00>
<00>
<00>

7
f
<00>
<00>
<00>
<00>
<00>
<00>
	
"	
3	
b	
~	
<00>	
<00>	
<00>	
<00>	
<00>	
<00>	
<00>	




(

W

s

<00>

<00>

<00>

<00>


I
e
<00>
<00>
<00>
<00>
*
F
u
<00>
<00>
<00>


'

8

I

Z

k

<00>

<00>

<00>

<00>

<00>

<00>

)
E
V
g
x
<00>
<00>
<00>
<00>
<00>


G
c
t
<00>
<00>
<00>
<00>

C
Q
_
m
{
<00>
<00>
<00>
<00>
<00>
<00>


;

(
-
1;A
E
N
R
\
a
e;/q
u
~
<00>
<00>
<00>
<00>;<00>
<00>
<00>
<00>
<00>
<00>
<00>;<00>
<00>




;+
/
8
<
E
I
S
X
\;%l
p
y
}
<00>
<00>
<00>;6<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>;<00>
<00>
<00>;




 
*
/
3; C
G
P
T
]
a
k
p
t;:<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>;<00>
<00>
<00>
<00>
<00>
<00>
<00>;



"
&
0
5
9;*I
M
V
Z
c
g
q
v
z;B<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>

#
0
L
Y
q
~
<00>
<00>
<00>
<00>
<00>
<00>




-
1
B
F
W
[
l
p
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>








.

2

9

=

O

S

d

h

y

}

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>





#
5
9
K
O
`
d
u
y
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>




(
,
=
A
S
W
j
n
u
y
<00>
<00>



;
; 
$;(
,;







x
<00>
<00>

<00>:<00>:<00>:<00>:<00>:<00>:<00>:<00>:<00>:<00>:<00>:<00>:<00>:<00>::(:(:(:*(:*.:*4:5@:@I:@T:@\:Be:Bn:Bw:X}:X<00>:Z<00>:j<00>:j<00>:<00>:<00>:<00>:<00>:<00>:<00>:<00>:<00>:
<00>:<00>:::: : ): /: 5:#;:+G:6P:6X:6c:8k::t::}::<00>:P<00>:P<00>:R<00>:b<00>:b<00>:b<00>:f<00>:<00>:<00>:<00>:<00>:<00>:<00>::::#:+:4:=:F:L:X:!a:!i:!u:#}:%<00>:%<00>:%<00>:(<00>:-<00>:2<00>:2<00>:2<00>:4<00>:6<00>:6<00>:6<00>:A<00>:A<00>:F<00>:F:: :(:4:<:E:N:T:`:m:y:<00>:(<00>:+<00>:+<00>:+<00>:-<00>:/<00>:/<00>:/<00>::<00>:?<00>:?





$
0
<
H
T
`
l
x
<00>
<00>
<00>
<00>
<00>
<00>
<00>
.symtab.strtab.shstrtab.rela.literal.timer_hal_init.literal.timer_hal_deinit.literal.timer_hal_capture_and_get_counter_value.text.data.bss.rela.text.timer_hal_init.rela.text.timer_hal_deinit.text.timer_hal_set_counter_value.rela.text.timer_hal_capture_and_get_counter_value.rela.debug_frame.rela.debug_info.debug_abbrev.rela.debug_loc.rela.debug_aranges.rela.debug_ranges.rela.debug_line.debug_str.comment.xtensa.info.rela.xt.lit.rela.xt.prop 
4@6#
8
DR
L<00>
P
<00>
P
<00>P
<00>
Pl<00>@ 6H#<00>
<00>h<00>@h6#
<00>
$
H<00>
l
A<00>@<00>6#
$

<00>
p
@<00>6<00>#6

 
1
@<00>7`#B

1<00>
U

<00><00>
P
@<00>FP#e

<00>8
`
@DKl#y

<00>(
t
@<00>K`#<00>

<00><00>
<00>
@L#<00>

0<00>%<00>

<00>

0I20

<00>
y28
<00>

<00>2
<00>
@R$#<00>

<00>2<00>
<00>
@4R<00>#!
<00>3<00>
$	<00>5<00>
S<00>

/0              0           0     0     644     7532      `
ELF



^
$4(TIMG0T0TIMG0T1TIMG1T0TIMG1T1y
t<0C><00>	
N
7<05><05><07>ZmintU<07><04>
<08>oa"<06>
<06>	
<06><06><06>~
<06>}<06>
	<06>

3<06><06>
 {<06><06>#
<06>
<06><06>
<06><06>EW	<06><06>

<06>2
<06> h!}"<06>
#8$p%&"';	(+<06>
,<06>-<06>.G/=0"	123H4		5A6<06>
7!8<06>9
:G
;<06><#=t><06>
?k@AA*B7Ce
D@
Eva
<0E>3R
<06>
<06>	<06>
h <06>	a
T
<06>N
<06><06>f(<04>a<04>[
<06>_q	Z|
<06><06>
<06>	_
<06><06>
		6
"
<EFBFBD>"<22>
P	\6B]a
a
G
c
-]b
	&

%$>$>&I
>I:;9
(I:;9I	
:;9


:;9I8

I
!I/
4:;9I?<4G:;9G
A



<01>






/home/ricardo/.espressif/v6.1/esp-idf/components/esp_hal_timg/esp32/home/ricardo/.espressif/v6.1/esp-idf/components/soc/esp32/include/soc/home/ricardo/.espressif/v6.1/esp-idf/components/esp_hal_timg/include/haltimer_periph.c
interrupts.hperiph_defs.hclk_tree_defs.htimer_periph.hmodule_nameETS_RWBLE_INTR_SOURCEETS_PWM0_INTR_SOURCEETS_MPU_IA_INTR_SOURCEPERIPH_BT_BASEBAND_MODULEPERIPH_HSPI_MODULEETS_TG0_T1_LEVEL_INTR_SOURCEcharETS_I2S0_INTR_SOURCEPERIPH_UHCI0_MODULEshort intETS_SPI2_INTR_SOURCEPERIPH_MODULE_MAXETS_FROM_CPU_INTR3_SOURCEPERIPH_SPI_MODULEETS_TG1_T1_LEVEL_INTR_SOURCEETS_MAX_INTR_SOURCEPERIPH_BT_MODULEETS_CACHE_IA_INTR_SOURCEETS_BT_BB_NMI_SOURCEETS_WDT_INTR_SOURCEETS_EFUSE_INTR_SOURCEETS_TG1_T1_EDGE_INTR_SOURCEETS_UART1_INTR_SOURCEETS_GPIO_INTR_SOURCEsoc_timg_gptimer_signal_desc_tETS_TG0_LACT_EDGE_INTR_SOURCEETS_SPI3_DMA_INTR_SOURCElong long intETS_I2S1_INTR_SOURCEETS_RWBT_NMI_SOURCEETS_TWAI_INTR_SOURCESOC_MOD_CLK_XTAL32KSOC_MOD_CLK_RTC_FASTlong intETS_TG0_WDT_LEVEL_INTR_SOURCEETS_TG1_LACT_LEVEL_INTR_SOURCEETS_LEDC_INTR_SOURCEETS_MMU_IA_INTR_SOURCEETS_TG1_LACT_EDGE_INTR_SOURCESOC_MOD_CLK_RTC_SLOWETS_TG1_T0_EDGE_INTR_SOURCEETS_UHCI0_INTR_SOURCESOC_MOD_CLK_REF_TICK/home/ricardo/.espressif/v6.1/esp-idf/components/esp_hal_timg/esp32/timer_periph.cSOC_MOD_CLK_APLLETS_ETH_MAC_INTR_SOURCEunsigned charETS_FROM_CPU_INTR1_SOURCESOC_MOD_CLK_XTALETS_SDIO_HOST_INTR_SOURCElong doubleETS_GPIO_NMI_SOURCEPERIPH_RNG_MODULEPERIPH_PHY_CALIBRATION_MODULEETS_TG0_LACT_LEVEL_INTR_SOURCESOC_MOD_CLK_INVALIDPERIPH_TIMG0_MODULEETS_TIMER1_INTR_SOURCEETS_UART2_INTR_SOURCEsigned charSOC_MOD_CLK_PLL_D2long long unsigned intunsigned intETS_SPI0_INTR_SOURCEETS_TG0_WDT_EDGE_INTR_SOURCEparent_moduleETS_FROM_CPU_INTR0_SOURCEETS_WIFI_BB_INTR_SOURCEshort unsigned intETS_TG1_T0_LEVEL_INTR_SOURCEPERIPH_UART1_MODULEETS_RMT_INTR_SOURCESOC_MOD_CLK_CPUETS_TG1_WDT_EDGE_INTR_SOURCEETS_UHCI1_INTR_SOURCEPERIPH_I2S0_MODULEETS_RWBT_INTR_SOURCEETS_BT_BB_INTR_SOURCEETS_RTC_CORE_INTR_SOURCEETS_TIMER2_INTR_SOURCEETS_RSA_INTR_SOURCEPERIPH_VSPI_MODULEETS_SLC1_INTR_SOURCEETS_SPI1_DMA_INTR_SOURCEPERIPH_WIFI_MODULEGNU C23 15.2.0 -ftls-model=local-exec -mdynconfig=xtensa_esp32.so -mlongcalls -gdwarf-4 -ggdb -Og -std=gnu23 -fno-builtin-memcpy -fno-builtin-memset -fno-builtin-bzero -ffunction-sections -fdata-sections -fno-shrink-wrap -fstrict-volatile-bitfields -fno-jump-tables -fno-tree-switch-conversion -fzero-init-padding-bits=all -fno-malloc-dcelong unsigned intETS_BT_MAC_INTR_SOURCESOC_MOD_CLK_RC_FAST_D256ETS_SPI2_DMA_INTR_SOURCEETS_I2C_EXT0_INTR_SOURCEETS_PWM1_INTR_SOURCEirq_idETS_FROM_CPU_INTR2_SOURCESOC_MOD_CLK_APBETS_WIFI_MAC_NMI_SOURCEPERIPH_TIMG1_MODULE/home/ricardo/ElectroNext/Projects/Reflow plate/esp-idf-firmware/Reflow-plate/buildETS_SPI1_INTR_SOURCEETS_TG0_T0_EDGE_INTR_SOURCEETS_SPI3_INTR_SOURCEETS_TG0_T1_EDGE_INTR_SOURCEsoc_timg_gptimer_signalsSOC_MOD_CLK_PLL_F160MSOC_MOD_CLK_RC_FASTETS_RWBLE_NMI_SOURCEETS_WIFI_MAC_INTR_SOURCEETS_TG1_WDT_LEVEL_INTR_SOURCEETS_SLC0_INTR_SOURCEETS_I2C_EXT1_INTR_SOURCEETS_TG0_T0_LEVEL_INTR_SOURCEETS_PCNT_INTR_SOURCEPERIPH_UART2_MODULEshared_periph_module_tETS_UART0_INTR_SOURCEPERIPH_WIFI_BT_COMMON_MODULEGCC: (crosstool-NG esp-15.2.0_20251204) 15.2.0 
Xtensa_InfoUSE_ABSOLUTE_LITERALS=0
ABI=0
(
<00><>
	

0timer_periph.csoc_timg_gptimer_signals


$






 
'
.
5
<
C
J
Q
d
k
r
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>










 

&

,

2

8

>

D

J

P

V

\

b

h

n

t

z

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>

<00>







7
=
C
I
O
U
[
a
g
m
s
y

<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>
<00>


)
7
c
x


.symtab.strtab.shstrtab.text.data.bss.rodata.str1.4.rela.rodata.soc_timg_gptimer_signals.rela.debug_info.debug_abbrev.rela.debug_aranges.debug_line.debug_str.comment.xtensa.info.rela.xt.prop
4
!
4
'4
,
24 
@
T0;@l0f
<00>}
a@<00><00>r

<00>
<00>
<00>
<00>@<
<00>
<00>K

<00>
0<00>

<00>
0<00>0

<00><00>8
<00>
1
<00>@H
@
	@)
T<00>