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Reflow-plate/build/bootloader/esp-idf/esp_security/libesp_security.a

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2026-09-13 20:50:51 +00:00
!<arch>
/ 0 0 0 0 314 `
<14><14><14><14>ITesp_crypto_sha_aes_lock_acquireesp_crypto_sha_aes_lock_releaseesp_crypto_mpi_lock_acquireesp_crypto_mpi_lock_releaseesp_crypto_aes_enable_periph_clkesp_crypto_sha_enable_periph_clkesp_crypto_mpi_enable_periph_clk__DECLARE_RCC_ATOMIC_ENVesp_crypto_common_clk_enable// 74 `
esp_crypto_lock.c.obj/
esp_crypto_periph_clk.c.obj/
esp_crypto_clk.c.obj/
/0 0 0 0 644 4712 `
ELF^04(6A<1D>6A<1D>6A<1D>6A<1D> <00><><EFBFBD><EFBFBD>|     <00> p!<08><07> <07><05><07>int<07><04><01>T<01><04><01><05><01><06><01>% U$ > $ > .?: ; 9 '.?: ; 9 ' .1@<18>B4<00>k<01> /home/ricardo/.espressif/v6.1/esp-idf/components/esp_security/srcesp_crypto_lock.c,<03>-  <03> <03> <03> /home/ricardo/.espressif/v6.1/esp-idf/components/esp_security/src/esp_crypto_lock.cesp_crypto_mpi_lock_acquire/home/ricardo/ElectroNext/Projects/Reflow plate/esp-idf-firmware/V0.1/build/bootloaderunsigned charlong unsigned intshort unsigned intesp_crypto_sha_aes_lock_releaseGNU C23 15.2.0 -ftls-model=local-exec -mdynconfig=xtensa_esp32.so -mlongcalls -mno-target-align -gdwarf-4 -ggdb -Os -std=gnu23 -fno-builtin-memcpy -fno-builtin-memset -fno-builtin-bzero -ffunction-sections -fdata-sections -freorder-blocks -fstrict-volatile-bitfields -fno-jump-tables -fno-tree-switch-conversion -fno-stack-protector -fzero-init-padding-bits=all -fno-malloc-dceunsigned intesp_crypto_mpi_lock_releaselong long unsigned intlong long intesp_crypto_sha_aes_lock_acquireshort intlong intlong doublesigned charGCC: (crosstool-NG esp-15.2.0_20251204) 15.2.0 Xtensa_InfoUSE_ABSOLUTE_LITERALS=0
ABI=0
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<    j   ETS_FROM_CPU_INTR3_SOURCEesp_crypto_sha_enable_periph_clk/home/ricardo/.espressif/v6.1/esp-idf/components/esp_security/src/esp_crypto_periph_clk.cETS_MMU_IA_INTR_SOURCEETS_TG0_T0_LEVEL_INTR_SOURCEETS_SPI3_DMA_INTR_SOURCElong long unsigned intETS_TG0_WDT_LEVEL_INTR_SOURCEETS_CACHE_IA_INTR_SOURCEETS_TIMER1_INTR_SOURCEETS_PCNT_INTR_SOURCElong long intsigned charesp_crypto_common_clk_enableETS_RMT_INTR_SOURCEsha_ll_reset_registerETS_TG1_T0_EDGE_INTR_SOURCEETS_RWBT_INTR_SOURCElong intETS_UART1_INTR_SOURCEETS_WIFI_BB_INTR_SOURCEETS_RWBT_NMI_SOURCEesp_crypto_mpi_enable_periph_clkenableETS_TG1_T0_LEVEL_INTR_SOURCE__uint32_tETS_SDIO_HOST_INTR_SOURCEsha_ll_enable_bus_clockETS_WIFI_MAC_NMI_SOURCEunsigned intETS_LEDC_INTR_SOURCEETS_TG0_T0_EDGE_INTR_SOURCEETS_TG1_LACT_LEVEL_INTR_SOURCElong unsigned intGNU C23 15.2.0 -ftls-model=local-exec -mdynconfig=xtensa_esp32.so -mlongcalls -mno-target-align -gdwarf-4 -ggdb -Os -std=gnu23 -fno-builtin-memcpy -fno-builtin-memset -fno-builtin-bzero -ffunction-sections -fdata-sections -freorder-blocks -fstrict-volatile-bitfields -fno-jump-tables -fno-tree-switch-conversion -fno-stack-protector -fzero-init-padding-bits=all -fno-malloc-dceETS_PWM1_INTR_SOURCEETS_TIMER2_INTR_SOURCEshort unsigned intETS_SPI3_INTR_SOURCEETS_SPI2_DMA_INTR_SOURCE__DECLARE_RCC_ATOMIC_ENVETS_UHCI1_INTR_SOURCEETS_SPI1_DMA_INTR_SOURCEETS_FROM_CPU_INTR2_SOURCEETS_I2S0_INTR_SOURCEETS_UART2_INTR_SOURCEETS_BT_BB_NMI_SOURCEETS_TG0_T1_LEVEL_INTR_SOURCEETS_TG0_LACT_LEVEL_INTR_SOURCEmpi_ll_power_upaes_ll_reset_registerETS_TG0_T1_EDGE_INTR_SOURCEETS_TG1_T1_LEVEL_INTR_SOURCElong doubleETS_RTC_CORE_INTR_SOURCEETS_FROM_CPU_INTR1_SOURCEETS_BT_BB_INTR_SOURCEaes_ll_enable_bus_clockETS_I2C_EXT0_INTR_SOURCEETS_MAX_INTR_SOURCEETS_TG0_LACT_EDGE_INTR_SOURCEETS_SPI1_INTR_SOURCE_Boolunsigned charETS_RSA_INTR_SOURCEETS_TWAI_INTR_SOURCEETS_RWBLE_NMI_SOURCEshort intETS_MPU_IA_INTR_SOURCEmpi_ll_reset_registerETS_I2S1_INTR_SOURCEETS_SLC1_INTR_SOURCEETS_GPIO_NMI_SOURCEuint32_tETS_TG1_WDT_EDGE_INTR_SOURCEETS_WIFI_MAC_INTR_SOURCEETS_FROM_CPU_INTR0_SOURCEETS_TG1_WDT_LEVEL_INTR_SOURCEchar/home/ricardo/ElectroNext/Projects/Reflow plate/esp-idf-firmware/V0.1/build/bootloaderETS_WDT_INTR_SOURCEETS_EFUSE_INTR_SOURCEETS_TG1_LACT_EDGE_INTR_SOURCEETS_I2C_EXT1_INTR_SOURCEETS_PWM0_INTR_SOURCEETS_RWBLE_INTR_SOURCEETS_SPI2_INTR_SOURCEETS_BT_MAC_INTR_SOURCEmpi_ll_power_downETS_GPIO_INTR_SOURCEETS_UHCI0_INTR_SOURCEETS_SPI0_INTR_SOURCEesp_crypto_aes_enable_periph_clkETS_TG1_T1_EDGE_INTR_SOURCEETS_ETH_MAC_INTR_SOURCEETS_TG0_WDT_EDGE_INTR_SOURCEETS_UART0_INTR_SOURCEmpi_ll_enable_bus_clockETS_SLC0_INTR_SOURCEGCC: (crosstool-NG esp-15.2.0_20251204) 15.2.0 Xtensa_InfoUSE_ABSOLUTE_LITERALS=0
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ABI=0
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 esp_crypto_clk.cesp_crypto_common_clk_enable;;;!;    
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