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Reflow-plate/build/esp-idf/soc/libsoc.a

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2026-09-13 20:50:51 +00:00
!<arch>
/ 0 0 0 0 328 `
JJ&J<<3C>Z<>Z<>Z<>vv<00><><00><><00><>lldesc_setup_link_constrainedlldesc_get_received_lenesp_dport_access_read_bufferesp_isr_namesGPIO_HOLD_MASKGPIO_PIN_MUX_REG_OFFSETGPIO_PIN_MUX_REGesp_dport_access_reg_readesp_dport_access_sequence_reg_readMPI_OPERATIONS_REGMPI_BLOCK_BASESpower_supply_periph_signal// 130 `
dport_access_common.c.obj/
interrupts.c.obj/
gpio_periph.c.obj/
dport_access.c.obj/
mpi_periph.c.obj/
power_supply_periph.c.obj/
lldesc.c.obj/ 0 0 0 644 9156 `
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4: ; 9 I?< 4G: ; 9 <00><00><01> /home/ricardo/.espressif/v6.1/esp-idf/components/soc/esp32/home/ricardo/.espressif/tools/xtensa-esp-elf/esp-15.2.0_20251204/xtensa-esp-elf/picolibc/include/machine/home/ricardo/.espressif/tools/xtensa-esp-elf/esp-15.2.0_20251204/xtensa-esp-elf/picolibc/include/sys/home/ricardo/.espressif/v6.1/esp-idf/components/soc/include/soc/home/ricardo/.espressif/v6.1/esp-idf/components/soc/esp32/include/socmpi_periph.c_default_types.h_stdint.hmpi_periph.hinterrupts.hETS_TG1_LACT_EDGE_INTR_SOURCEETS_RWBLE_INTR_SOURCEETS_PWM0_INTR_SOURCEETS_MPU_IA_INTR_SOURCEETS_RMT_INTR_SOURCEETS_TG1_T0_LEVEL_INTR_SOURCEETS_TG0_T1_LEVEL_INTR_SOURCEETS_TG1_LACT_LEVEL_INTR_SOURCEshort intETS_SPI2_INTR_SOURCEETS_FROM_CPU_INTR3_SOURCE__uint32_tETS_TG1_T1_LEVEL_INTR_SOURCEETS_TG1_WDT_EDGE_INTR_SOURCEMPI_BLOCK_BASESETS_CACHE_IA_INTR_SOURCEETS_BT_BB_NMI_SOURCEETS_WDT_INTR_SOURCEETS_TG0_LACT_EDGE_INTR_SOURCEETS_EFUSE_INTR_SOURCEETS_UART1_INTR_SOURCEETS_FROM_CPU_INTR1_SOURCEETS_GPIO_INTR_SOURCEETS_TWAI_INTR_SOURCEETS_MAX_INTR_SOURCEETS_SPI3_DMA_INTR_SOURCElong long intETS_I2S1_INTR_SOURCEETS_RWBT_NMI_SOURCEETS_TG1_T1_EDGE_INTR_SOURCElong int/home/ricardo/.espressif/v6.1/esp-idf/components/soc/esp32/mpi_periph.cETS_LEDC_INTR_SOURCEETS_MMU_IA_INTR_SOURCEETS_RWBT_INTR_SOURCEETS_TG1_T0_EDGE_INTR_SOURCEETS_UHCI0_INTR_SOURCEETS_TIMER1_INTR_SOURCEETS_ETH_MAC_INTR_SOURCEETS_GPIO_NMI_SOURCEETS_SDIO_HOST_INTR_SOURCElong doubleunsigned charETS_UART2_INTR_SOURCEsigned charlong long unsigned intMPI_OPERATIONS_REGuint32_tunsigned intETS_SPI0_INTR_SOURCEETS_BT_BB_INTR_SOURCEETS_TG0_T1_EDGE_INTR_SOURCEETS_FROM_CPU_INTR0_SOURCEETS_WIFI_BB_INTR_SOURCEshort unsigned intETS_I2S0_INTR_SOURCEETS_TG0_T0_EDGE_INTR_SOURCEchar/home/ricardo/ElectroNext/Projects/Reflow plate/esp-idf-firmware/V0.1/buildETS_UHCI1_INTR_SOURCEETS_RTC_CORE_INTR_SOURCEETS_TIMER2_INTR_SOURCEETS_RSA_INTR_SOURCEETS_SLC1_INTR_SOURCEETS_SPI1_DMA_INTR_SOURCEETS_I2C_EXT0_INTR_SOURCEGNU C23 15.2.0 -ftls-model=local-exec -mdynconfig=xtensa_esp32.so -mlongcalls -gdwarf-4 -ggdb -Og -std=gnu23 -fno-builtin-memcpy -fno-builtin-memset -fno-builtin-bzero -ffunction-sections -fdata-sections -fno-shrink-wrap -fstrict-volatile-bitfields -fno-jump-tables -fno-tree-switch-conversion -fzero-init-padding-bits=all -fno-malloc-dcelong unsigned intETS_BT_MAC_INTR_SOURCEETS_SPI2_DMA_INTR_SOURCEETS_PWM1_INTR_SOURCEETS_FROM_CPU_INTR2_SOURCEETS_WIFI_MAC_NMI_SOURCEETS_SPI1_INTR_SOURCEETS_PCNT_INTR_SOURCEETS_SPI3_INTR_SOURCEETS_TG0_LACT_LEVEL_INTR_SOURCEETS_RWBLE_NMI_SOURCEETS_TG0_WDT_EDGE_INTR_SOURCEETS_TG0_WDT_LEVEL_INTR_SOURCEETS_WIFI_MAC_INTR_SOURCEETS_TG1_WDT_LEVEL_INTR_SOURCEETS_SLC0_INTR_SOURCEETS_I2C_EXT1_INTR_SOURCEETS_TG0_T0_LEVEL_INTR_SOURCEETS_UART0_INTR_SOURCEGCC: (crosstool-NG esp-15.2.0_20251204) 15.2.0 Xtensa_InfoUSE_ABSOLUTE_LITERALS=0
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