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Reflow-plate/build/esp-idf/esp_hal_clock/libesp_hal_clock.a

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First commit with working display
2026-09-13 20:50:51 +00:00
!<arch>
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<01><01><01><01><01><01><01><01>clk_hal_lp_slow_get_freq_hzclk_hal_xtal_get_freq_mhzclk_hal_apll_get_freq_hzclk_hal_soc_root_get_freq_mhzclk_hal_cpu_get_freq_hzclk_hal_apb_get_freq_hzclk_hal_clock_output_setupclk_hal_clock_output_teardown// 20 `
clk_tree_hal.c.obj/
Screen changed to landscape, #define to configure screen to landscape or portrait.
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First commit with working display
2026-09-13 20:50:51 +00:00
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Screen changed to landscape, #define to configure screen to landscape or portrait.
2026-09-13 21:56:13 +00:00
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First commit with working display
2026-09-13 20:50:51 +00:00
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Screen changed to landscape, #define to configure screen to landscape or portrait.
2026-09-13 21:56:13 +00:00
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First commit with working display
2026-09-13 20:50:51 +00:00
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Screen changed to landscape, #define to configure screen to landscape or portrait.
2026-09-13 21:56:13 +00:00
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First commit with working display
2026-09-13 20:50:51 +00:00
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Screen changed to landscape, #define to configure screen to landscape or portrait.
2026-09-13 21:56:13 +00:00
                <03>z  esp_log_level_tETS_EFUSE_INTR_SOURCEEXT_EVENT1_TRIGETS_SPI1_DMA_INTR_SOURCECLKOUT_SIG_XTALETS_SLC1_INTR_SOURCERESET_REASON_CPU1_SWCLKOUT_SIG_I2S0CLKOUT_SIG_I2S1ETS_WIFI_MAC_NMI_SOURCERESET_REASON_SYS_RTC_WDTsoc_cpu_clk_src_tETS_WDT_INTR_SOURCEPOWERON_RESET__assert_funcETS_TG1_T0_EDGE_INTR_SOURCESDIO_IDLE_INTclk_ll_bind_output_channelunsigned intETS_PWM0_INTR_SOURCEdis_timestampclk_hal_xtal_get_freq_mhznumeratorRESET_REASON_CORE_SDIOETS_UART1_INTR_SOURCEclk_ll_cpu_get_dividersoc_rtc_slow_clk_src_tUART1_TRIGclk_ll_apll_get_configETS_I2C_EXT1_INTR_SOURCEclk_hal_apb_get_freq_hzCLKOUT_CHANNEL_MAXREJECT_INTRESET_REASON_CPU1_RTC_WDTETS_BT_BB_NMI_SOURCEesp_log_timestampETS_SDIO_HOST_INTR_SOURCEETS_RWBT_NMI_SOURCEETS_TG1_LACT_EDGE_INTR_SOURCEETS_TG1_T1_LEVEL_INTR_SOURCEETS_RMT_INTR_SOURCEclk_siguint32_tNO_INTRESET_REASON_CPU1_MWDT1SOC_MOD_CLK_XTAL32KETS_SPI0_INTR_SOURCEclk_ll_cpu_get_divider_from_apllETS_SPI2_DMA_INTR_SOURCERESET_REASON_CPU1_CPU0clk_hal_ahb_get_freq_hzCLKOUT_SIG_PLL_F80MESP_LOG_MAXlong long unsigned intSOC_MOD_CLK_RTC_FASTDEEPSLEEP_RESETETS_FROM_CPU_INTR0_SOURCESAR_TRIGdis_colorRTCWDT_CPU_RESETETS_FROM_CPU_INTR3_SOURCEETS_SPI2_INTR_SOURCEclk_hal_clock_output_setupESP_LOG_WARNETS_SPI3_DMA_INTR_SOURCETG1WDT_SYS_RESETETS_TG0_T1_EDGE_INTR_SOURCEETS_TG0_LACT_EDGE_INTR_SOURCEETS_RTC_CORE_INTR_SOURCEETS_TG0_LACT_LEVEL_INTR_SOURCEETS_BT_MAC_INTR_SOURCENO_SLEEPTG0WDT_SYS_RESETETS_I2S0_INTR_SOURCEconstrained_envETS_UHCI0_INTR_SOURCEesp_log_config_tETS_TG1_T0_LEVEL_INTR_SOURCEesp_logETS_RWBLE_NMI_SOURCESOC_MOD_CLK_RC_FAST_D256RESET_REASON_CORE_RTC_WDTSW_RESET__uint64_tSDIO_RESETEXT_EVENT0_TRIGESP_LOG_NONEfreqEXT_CPU_RESETSOC_CPU_CLK_SRC_APLLsdm2CLKOUT_SIG_INVALIDTOUCH_TRIGRTC_TIME_VALID_INTSOC_MOD_CLK_RC_FASTcpu_freq_selSOC_XTAL_FREQ_24Mesp_dport_access_reg_readcharclk_hal_clock_output_teardownCLKOUT_SIG_PLLregi2c_ctrl_read_reg_maskCLKOUT_SIG_RC_SLOWETS_TG0_T0_EDGE_INTR_SOURCEETS_TG0_WDT_EDGE_INTR_SOURCEETS_TG1_WDT_LEVEL_INTR_SOURCESOC_RTC_SLOW_CLK_SRC_INVALIDdataSOC_CPU_CLK_SRC_INVALIDRESET_REASON_CPU0_SWapll_freq_hzuint8_tlog_levelchannel_idSOC_RTC_SLOW_CLK_SRC_RC_SLOWETS_ETH_MAC_INTR_SOURCEETS_RWBT_INTR_SOURCECLKOUT_SIG_REF_TICKclk_hal_cpu_get_freq_hzSOC_RTC_SLOW_CLK_SRC_RC_FAST_D256long long intUART0_TRIGRTCWDT_BROWN_OUT_RESETSOC_CPU_CLK_SRC_XTALETS_FROM_CPU_INTR1_SOURCETGWDT_CPU_RESETETS_PWM1_INTR_SOURCEETS_TIMER2_INTR_SOURCESOC_MOD_CLK_CPUSOC_XTAL_FREQ_26MSOC_RTC_SLOW_CLK_SRC_DEFAULTETS_TG0_WDT_LEVEL_INTR_SOURCEcpu_clk_srcETS_LEDC_INTR_SOURCE/home/ricardo/ElectroNext/Projects/Reflow plate/esp-idf-firmware/Reflow-plate/buildESP_LOG_INFOSOC_CPU_CLK_SRC_PLLETS_MPU_IA_INTR_SOURCETIMER_EXPIRERESET_REASON_CHIP_POWER_ONETS_TWAI_INTR_SOURCESOC_MOD_CLK_PLL_D2clk_hal_apll_get_freq_hzETS_UART0_INTR_SOURCEETS_SLC0_INTR_SOURCEclk_ll_cpu_get_freq_mhz_from_pllETS_MAX_INTR_SOURCEETS_I2C_EXT0_INTR_SOURCEETS_RWBLE_INTR_SOURCEETS_GPIO_INTR_SOURCEETS_WIFI_BB_INTR_SOURCElong doubleclk_ll_rtc_slow_get_srcRESET_REASON_CPU0_MWDT0ETS_GPIO_NMI_SOURCEclk_hal_lp_slow_get_freq_hzclk_hal_soc_root_get_freq_mhzETS_UART2_INTR_SOURCEclk_ll_xtal_load_freq_mhzETS_CACHE_IA_INTR_SOURCEclock_out_channelxtal_freq_regsdm0sdm1short intdividerlong intETS_WIFI_MAC_INTR_SOURCEETS_SPI3_INTR_SOURCEETS_TG0_T1_LEVEL_INTR_SOURCE__udivdi3RTC_WDT_INTSW_CPU_RESETuint64_tCLKOUT_CHANNEL_1CLKOUT_CHANNEL_2CLKOUT_CHANNEL_3SOC_MOD_CLK_APBSOC_MOD_CLK_APLLxtal_freq_hzETS_SPI1_INTR_SOURCEo_divETS_RSA_INTR_SOURCEdenominator__uint8_tsourceoptsRTCWDT_SYS_RESETSOC_RTC_SLOW_CLK_SRC_XTAL32KETS_TG1_LACT_LEVEL_INTR_SOURCEWAKEUP_INTGPIO_TRIGRTCWDT_RTC_RESETlong unsigned intNO_MEANESP_LOG_VERBOSEclk_ll_cpu_get_srcCLKOUT_SIG_RC_FASTRESET_REASON_CORE_SWRESET_REASON_CORE_DEEP_SLEEPSDIO_TRIGunsigned char__uint32_tETS_MMU_IA_INTR_SOURCEbinary_modeCLK_HAL_TAGSOC_XTAL_FRE
First commit with working display
2026-09-13 20:50:51 +00:00
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Screen changed to landscape, #define to configure screen to landscape or portrait.
2026-09-13 21:56:13 +00:00
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